Hierarchical Gate-Array Routing on a Hypercube Multiprocessor

Gate-arrays are the most common design style for semicus-tom VLSI integrated circuits. An important part of the gate-array design process is the routing of wires between the logic elements, which is an extremely compute-intensive operation. This paper presents an algorithm for routing gate-arrays that uses a hypercube connected parallel processor to provide the necessary computation power. In order to make optimal use of the hypercube, the routing algorithm is organized so that inter-processor communication is kept to a minimum. It occurs only during the global routing and crossing placement phases of the algorithm, which constitute less than 15% of the total running time of the algorithm. On the basis of the results of executing the algorithm on two gate-array benchmarks the case is made for using hypercuhe multiprocessors as accelerators for compute-intensive CAD operations. 0 1990Academic press, inc.